Integrated circuit (IC) fabrication processes have produced ICs with reduced node spacing in the range of 48 nm and 28 nm nodes, for example. Material having an extremely low dielectric constant (ELK) has been used to accommodate the reduced node spacing and to enhance electrical performance of the ICs that are produced with such small node spacing. The ELK material may include relatively porous material which may be susceptible to cracking in response to certain stresses.
Interconnect pillars constructed from more rigid conductive materials such as copper have been used along with solder in certain solder bump connections between a semiconductor die and a substrate. In electronic packaging, for example, a flip chip can include a pillar that extends from a contact on a die or wafer to a solder connection on a substrate. The solder connection can be a solder on pad (SOP) connection, for example.
The use of pillars provides an improvement over earlier semiconductor interconnect techniques by allowing a very high density of interconnects. The metallurgical properties of the pillars compared to earlier solder structures allow the smaller pitch connections to maintain an appropriate standoff distance between a semiconductor die and a substrate to which it is connected. The use of copper pillars also reduces electromigration (EM) in the interconnects. However, the use of copper pillars can make a backend silicon structure more susceptible to cracking during package assembly.
During the processing of flip chips, the substrate and semiconductor die are subject to substantial heating and cooling. The semiconductor die may be constructed from a material such as silicon which has a coefficient of thermal expansion (CTE) of about 2.6×10−6/° C. and the substrate may have a CTE in the range of about 15×10−6/° C. to about 17×10−6/° C. The CTE mismatch between the substrate and die causes the substrate to expand and contract more than the die during a heating and cooling cycle. In packages that include interconnects with copper pillars rather than traditional solder bumps to accommodate finer bump pitch, the copper of the pillars may not be able to deform enough to take up the stress caused by the thermal expansion mismatch between the die and substrate. The higher Young's modulus of the copper pillar causes more of the stress to be “transferred” to the sensitive ELK layers of the die. This increases the chance for ELK layer cracking for flip chip type interconnects. Such cracking due to high stress in the Extremely Low Dielectric Constant (ELK) layers is a common failure of semiconductor packages.